1. Field of the Invention
The present invention relates to a semiconductor wafer and, in particular, a semiconductor wafer having an IC (integrated circuit) pattern formed therein.
2. Description of the Related Art
FIG. 1 shows a portion of a conventional semiconductor wafer having an IC pattern formed therein. In FIG. 1, reference number 31 shows a dicing line area; reference number 32 shows a plurality of chip areas into which a wafer is divided by the dicing line area 31; and reference number 33 shows a plurality of pads formed over the respective chip area 32.
During the manufacture of a semiconductor integrated circuit, die-sort testing has been done with the measuring terminals (probe needles) of a die-sort machine's probe card, not shown, placed in contact with corresponding pads 33 on the chip areas 32 to examine the function of the IC chips on the semiconductor wafer.
If the chip areas 32, have a large number of output pads 33 formed thereon, the same number of measuring terminals are required on the probe card of the die-sort machine for use in the die-sort test. That is, many measuring terminals are for a large number of pads 33. For this reason, it becomes very difficult to produce a corresponding probe card. Further, the number of relay switches is remarkably increased in the die-sort machine, requiring a very complex, expensive die sort machine.
With a recent technological progress, a higher packing density IC pattern and smaller IC chip size have been seen as a recent trend. For a semiconductor circuit chip having a larger number of pads, the pad size and pitch become smaller and smaller. For this reason, the probe needles on the die-sort machine's probe card become correspondingly miniaturized and difficulty is encountered in placing the probe needles in contact with the corresponding pads. It takes a longer time to perform such an operation and hence to perform die-sort testing.